1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device and its manufacturing method in which a leak current between elements due to a parasitic transistor formed at an element isolation part is reduced by using an SOI (Silicon On Insulator) substrate as a semiconductor substrate and using a LOCOS (Local Oxidation of Silicon) method as an element isolation technology for the SOI substrate.
2. Description of the Related Art
Recently, for the purpose of improving a threshold characteristic and reducing a parasitic capacity, an SOI substrate with a silicon layer formed on an insulative layer called BOX oxide film is in heavy usage as a substrate to form a semiconductor element.
Element isolation is implemented on the silicon layer (SOI layer) by a trench structure (trench isolation method) or a LOCOS method. A MOSFET element on the SOI substrate is manufactured on the SOI substrate through a process similar to the one of manufacturing a conventional MOSFET element. The manufacturing process of MOSFET element on an SOI substrate using a LOCOS method will be explained as follows.
Element isolation by a LOCOS method is disclosed in the document “J. W. Thomas et al., Proceedings IEEE Intr. SOIconf., 116 (1995)”. First, according to the document, an oxide film to be a pad oxide film is formed on an SOI substrate. Second, patterning is implemented by a conventional photolithography method using a resist as an optical mask after a nitride film is accumulated. And then the pad oxide film and the nitride film in an element isolation region are removed.
Next, heat treatment is implemented to form a field oxide film (LOCOS oxide film) in an element isolation region. Due to the limit of the thickness of SOI layer, the field oxide layer does not become far thicker than the SOI layer, different from that of a MOSFET with bulk structure. After forming the LOCOS oxide film, the nitride film and the pad oxide film are removed. After that, a gate oxide film, an electrode, a source and a drain are formed similar to the process of manufacturing a conventional MOSFET.
The manufacturing process as explained above is only one example, and there are some modifications of the process in which, for example, an LDD (Lightly Doped Drain) structure is formed in forming a MOSFET with a conventional substrate. However, the explanations of the modifications are omitted here since the explanations have no relation with the substance of the present invention.
In this LOCOS method, an edge region, a silicon layer, with the section of triangular shape, is formed between a BOX oxide film and the LOCOS oxide film, and the layer becomes a parasitic MOSFET. This parasitic MOSFET has a bad influence on the MOSFET element, a leak current is increased and a hump characteristic in which a hump seems to be at a current characteristic of the element is caused. For this reason, the threshold voltage in the MOSFET with the parasitic MOSFET becomes lower than the one in the MOSFET without the parasitic MOSFET.
On the other hand, a trench structure in which a silicon layer is etched to form a groove and in which an oxide film is embedded in the groove is disclosed in the document “IEEE ELECTRON DEVICE LETTERS, VOL. 6, JUNE 1995” and so on. Also, there is disclosed in the document “S-W Kang IEEE EDL-16, no. 6 1995” that the trouble of hump characteristic causing trouble in the LOCOS method can be resolved by the trench structure (trench isolation method).
The trench isolation method, however, needs to include a step of forming a groove in an element isolation region and removing an oxide film deposited on the part other than the groove, which increases the manufacturing steps comparing to the LOCOS method and makes the manufacturing cost high. For this reason, the isolation method cannot be employed to an element with low cost needed.
In view of this problem, a method of improving the hump characteristic using the LOCOS method is disclosed in the following patent documents. A method of improving a LOCOS edge shape on which a parasitic MOSFET is formed is disclosed in Japanese Patent Laid-open Publication No. 2000-306994 and a method of preventing a parasitic MOSFET from turning on by implanting an impurity into an edge region to increase an edge concentration is disclosed in Japanese Patent Laid-open Publication No. 2003-124303.
Also, a method of restraining a leak current by implanting an impurity by forming a groove in a LOCOS isolation region is disclosed in Japanese Patent Laid-open Publication No. 07-115125, and a method of reducing a leak current in an element isolation method in an element isolation method using the trench structure is disclosed in Japanese Patent Laid-open Publication No. 01-138730 and Japanese Patent Laid-open Publication No. 2001-148418. Further, a structure with fluorine implanted into a gate insulating film so that the concentration distribution can be appropriate, for the purpose of improving a dielectric breakdown resistance, is disclosed in Japanese Patent Laid-open Publication No. 2001-102571.
However, even those methods cited above are employed to the element isolation using the LOCOS method, the hump characteristic cannot be completely restrained, and, in a method of increasing an edge concentration by implanting an impurity into an edge region, the impurity in the edge region is diffused into the element part to have a bad influence on the characteristic of the element.